114 granted and pending patents across 17 invention families in 24 territories. 18 registered trademarks. The result of ten years of deliberate, physics-first development — filed before the market understood what it was looking at.
All figures from the official SFN patent and trademark register, April 2026. Patent protection spans the world's key semiconductor manufacturing and market jurisdictions. The estate covers device physics, process technology, logic architecture, memory architecture, fabrication systems, and the Centian Loop learning architecture.
The IP estate is broad by design — not one idea filed in many countries, but 21 distinct inventions each protected across multiple jurisdictions. The families span every layer of the SFN technology stack.
Quantum Zener tunnelling device architecture. The foundational device physics of the entire stack. Filed across 14+ jurisdictions.
Hair-trigger transistor — the balanced bipolar/unipolar switching architecture. Filed across 24 territories including US, China, Japan, Korea, Taiwan.
Vertical ZPOLAR Tunnel Logic. Granted in UK, Brazil, China, Europe, Indonesia, India, USA and more.
Vertical ZPOLAR architecture. Granted in UK, Taiwan, Eurasia. Pending in major remaining jurisdictions.
Enables a chip to incorporate a computer. Granted across China, Europe, Hong Kong, Israel, India, Japan, Korea, USA.
International PCT patent. Processing unit architecture built on BIZEN® physics.
Tunnel variant of BIZEN® device architecture. Granted in Europe, Taiwan, USA. Filed internationally.
High-speed BIZEN® variant. Granted in Europe, Ireland, and internationally via PCT.
High voltage transistor guard ring architecture — IGBT replacement. Granted across Australia, China, Europe, India, Russia, USA.
Power transistor architecture. Granted in China, Europe, Ireland, India, USA and internationally via PCT.
The fabrication process enabling BIZEN® device production. Granted in India. Pending in China, Europe, Hong Kong, USA.
Flip chip architecture for RFID applications. Granted in UK.
Next-generation BIZEN® architecture. Granted in USA. Pending in China, Europe, Hong Kong, Korea.
Next-generation ZPOLAR® architecture. Granted in Taiwan. Pending in China, Hong Kong.
Divisional European patent application — expanding coverage of the BIZEN® Tunnel family.
4 UK patents covering the SILO same-day atomic-layer additive fabrication platform. Filed 2025–2026.
Extended ZPOLAR® logic architecture. UK and Taiwan applications filed 2025.
Centian Execution Unit — the compute architecture supporting iterative hardware improvement through a controlled AI/fabrication feedback loop. Filed April 2026.
Non-volatile, vertically integrated memory architecture that scales through depth rather than geometry. Compatible with SILO and Centian Loop. Filed March 2026.
Tunnel mechanics in space environments. International coverage.
High voltage power device guard ring architecture. European coverage.
Two significant new patents filed in early 2026 — covering the Centian Loop compute architecture and the Domain-Wall Memory system. The IP estate continues to grow alongside the operational programme.
A compute architecture designed to support iterative hardware improvement through a controlled feedback loop between artificial intelligence, hardware design, fabrication, and execution. The architecture formalises the Centian Loop as a patented system — not a concept, but a protected invention. Human authorisation governs each cycle; capability compounds across iterations.
A non-volatile, vertically integrated memory architecture whose density increases through additional deposition cycles rather than additional lithographic complexity. Scales through depth, not geometry — making it naturally compatible with SILO fabrication and the Centian Loop's rapid iteration framework. "CMOS scales through geometry, months and masks. BIZEN® scales through depth, cycles and repetition."
Patent protection covers the world's key semiconductor manufacturing nations and end markets — not just the home jurisdiction.
The brand is protected as well as the technology — across key markets and in multiple forms (word marks, stylised marks, figurative marks).
Registered in UK, Europe, China, Hong Kong, India, USA, and Madrid Protocol international
GrantedRegistered in UK
GrantedRegistered in UK, Europe, China, USA. Pending in India.
GrantedRegistered in UK
GrantedApplication published UK — filed 3 April 2026
PendingApplication published UK — filed 3 April 2026
PendingApplication published UK — filed 5 April 2026
PendingApplication published UK — filed 29 March 2026
PendingFiled before the market understood what it was looking at. The IP estate is the result of ten years of deliberate, physics-first development.
These are not isolated patents. They are a progression: a new foundation, logic that needs fewer transistors, the devices to make it practical, building in 3D, then same-day manufacturing — and finally a loop that uses each result to improve the next.
Earliest public identity of the semiconductor platform — the foundation for the wider technology ecosystem.
An early alternative device architecture showing it was possible to move beyond conventional CMOS assumptions.
An early computing architecture built around the emerging semiconductor platform — expanding from devices into systems.
A route to reducing transistor count through alternative logic, not just geometric scaling. The foundational patent family.
Manufacturing methods to turn device concepts into repeatable fabrication — theory toward manufacturability.
Logic functions implemented directly within atomic-scale tunnel interfaces — central to transistor-count reduction.
Methods for increasing switching speed — the idea that speed could compound logic-density improvements.
Improved control and isolation structures — increased practicality and robustness.
A transistor architecture making tunnel-based logic practical via fast, low-voltage switching.
Additional device architectures extending the ZPOLAR family — expanding the design space.
Direct integration of tunnel logic with the ZPOLAR architecture — a more complete whole.
Three-dimensional extensions — increased integration density and future scaling options.
Compresses development cycles from months to days. The enabling technology that makes the Self-Learning Loop practical.
A memory scaling path based on depth rather than geometry — scaling through layers and fabrication cycles.
Hardware designed to improve through repeated manufacturing and operational feedback — hardware as a managed improvement cycle.
AI, hardware design, manufacturing and testing combined into one controlled iterative improvement system.
Dates are patent/trademark filing dates from SFN's records. Filings represent protected inventions and development milestones, not product releases.
Across the rest of the site we describe what our technology does, not our internal names for it. For technical readers, this is what those names refer to.
Our blueprint facility at 107 Station Street, Burton-on-Trent. Its purpose is to run and prove the Self-Learning Loop, not to make product — production is what the facilities franchised from it are for. It is the original working facility, and the model the rest are built from.
Single 3D Lithography — our low-temperature, mask-free same-day manufacturing process.
Our semiconductor platform. Tunnel-based logic at atomic interfaces; reduces transistor count through logic implementation, not just smaller geometry.
Our switching device technology — focuses on switching behaviour, speed and device operation.
Our 3D device architecture — combines our device technologies vertically in three dimensions.
The human-supervised design-build-test-improve cycle.
Our model for deploying manufacturing capability as a distributed network.
Domain-Wall Memory — non-volatile memory built in the same manufacturing run as the logic.
The direction of improvement that emerges from the loop. A = atomic manufacturing (low-temperature manufacturing, SILO and the implementation of BIZEN); Z₁ = BIZEN logic; Z₂ = ZPOLAR switching.
For a fuller technical explanation, see the technical deep dive.
Watch the Centian Loop® run. See same-day fabrication at FAB 107. Discuss franchise deployment. A private demonstration for qualified organisations.